1. Field of the Invention
The present invention relates to analyzing and resolving timing issues on an integrated circuit, and more particularly to an integrated circuit timing debug apparatus and method for dynamically changing the skew of a core clock signal on an integrated circuit for a controllable number of clock cycles to facilitate isolation and analysis of data hold/setup timing problems.
2. Description of the Related Art
Integrated circuit designers have employed simulation and/or test to identify, isolate, and analyze timing problems on a chip, which often resulted in a chip design that at best could not perform at target clock speeds and that at worst had to be modified prior to mass fabrication. Typically, register logic within each logic block of the chip is employed to transmit/receive data to/from a succeeding/preceding logic stage. Setup time problems occur when a given logic block exhibits a critical delay path with regard to operations performed within to the extent that, at a given clock speed, valid data is not provided to the next logic stage until after a clock edge occurs at the next logic stage that is intended to latch the data. A hold time problem is exhibited by a logic chain when the given logic block provides valid data to the next logic block but the data becomes invalid prior to a clock edge occurring at the next logic block that is intended to latch the data. In the setup time problem case, the latching clock edge at the next logic stage occurs too soon for the transfer of valid data. In the hold time problem case, the latching clock edge at the next logic stage occurs too late for the transfer of valid data.
FIG. 1A is a simplified block diagram showing a circuit 100 with two representative successive logic blocks 101 and 103 to which clock signals are provided. The first logic block 101 (LOGIC BLOCK 1) receives a first clock signal ELCK1 and provides data signals DATA to the second logic block 103 (LOGIC BLOCK 2), which receives a second clock signal ECLK2. FIG. 1B is a timing diagram illustrating operation of the circuit 100 for synchronized versus skewed clock signals. The timing diagram generally shows traces of the ELCK1, ECLK2 and DATA signals versus time. Particular time points are shown, including times T1, T2, T3, T4, and T5 occurring in sequential order.
The first two traces of the timing diagram show the case when the ECLK1 and ECLK2 clock signals are synchronized illustrating a setup time problem. As shown, for example, the ECLK1 and ECLK2 signals have synchronous edges including substantially coincident falling edges at time T1 and substantially coincident rising edges at time T3. The third trace shows the relative timing of the DATA signals from the first logic block 101 in which the DATA signals switch and become valid at a time T4, which is after time T3. The synchronized clock case illustrates a setup time problem in which the first logic block 101 exhibits a critical delay path such that valid data on the DATA signals at time T4 is not provided to the logic block 103 until after the rising clock edge at time T3 occurs. Because there is more work delay in the logic block 101 than there is time in a clock cycle, upon the rising edge of ECLK2 at time T3, invalid data is clocked into the logic block 103.
The fourth and fifth traces of the timing diagram show the case when the ECLK2 signal is skewed relative to the ECLK1 signal. In particular, the fourth trace is a trace of the ECLK1 signal substantially similar to the first trace of ECLK1. The fifth trace shows ECLK2 skewed relative to ECLK1 where the falling edge of ECLK2 occurs at time T2 after time T1 and the subsequent rising edge of ECLK2 occurs at a time T5 after the time T4. The skewed clocks case illustrates that by delaying ECLK2 relative to ECLK1, the setup time problem is eliminated. In particular, the rising edge of ECLK2 is delayed until after the DATA signals become valid, thus allowing a valid transfer of data from the first logic block 101 to the second logic block 103.
Designers have heretofore provided hardwired logic, such as fuses and one-time programmable logic devices, to skew the clocks that are provided to sequential logic blocks to solve critical path and hold time problems. Such solutions provided a clock skew fix that could not be changed after implementation without modifying the chip design. Also, with reference to the illustrated example, one of ordinary skill in the art will appreciate that ECLK2 can be delayed only in the event that there is delay margin associated with the second logic block 103. An alternative solution is to advance the clock for latching incoming data into the preceding logic block (e.g., logic block 101) so that more time is provided for the stage to perform its work. This alternative solution is not always feasible, however, and may result in new and unforeseen timing problems.
If the setup and hold problems described above occur, but not during every clock cycle, then identification and isolation of problem areas can be very complex indeed. Microprocessors, for example, are very much the types of pipelined systems where problems like this may be exhibited as a function of the flow of instructions that are executed. It is not inconceivable that a timing problem could occur on a single clock cycle well after initialization of the microprocessor. Yet a single timing error of this nature can cause failure of microprocessor operation. Skewing all cycles of a pipeline clock would be insufficient to identify and isolate timing problems that do not occur every clock cycle. In fact, skewing all cycles of a pipeline clock could potentially mask over periodic or one-time setup and hold problems.
As a matter of practice, designers analyze and simulate complex logic paths in an integrated circuit prior to committing a design to production. But one skilled in the art will appreciate that slight differences in clock skew cannot be simulated with sufficient accuracy and production process variations furthermore cannot be precisely modeled. Hence, fabricated integrated circuits often exhibit a number of unanticipated critical timing paths that designers are forced to address prior to shipment. Consequently, any setup time problems that occur after-the-fact (i.e., after the chip is fabricated and clock skews have been established) can only be eliminated by slowing down the clock speed of the device. Worse yet, after-the-fact hold time problems render a design totally inoperative. In either case, significant design modifications (often including changes to masks, electron beam analysis, etc.) are required to fix these types of problems.